Referring generally to information handling systems, they normally have as their main component a central processing unit (CPU), which directs all communications in the system and orchestrates all commands to be executed by the information handling system. Information handling systems also usually have a network, or networks, of physical connection devices called buses. These networks connect the CPU to any number of peripheral devices and components so that the CPU can communicate with the peripheral devices and components.
One type of bus that is used in information handling systems is a CPU local bus. Also referred to as a system bust the CPU local bus is specially designed for connecting the CPU directly to key components of the information handling system, such as the system memory and memory controller. A CPU local bus is a high performance bus, meaning that it executes data transfers between the CPU and the other components connected to the bus at a high rate of speed and can handle a multitude of data transfers simultaneously. Another type of bus found in an information handling system is a peripheral bus. Peripheral buses are designed to connect peripheral devices, such as input/output devices (I/O) and graphics packages, to the information handling system. Peripheral buses are normally connected to the CPU and the rest of the central components of the information handling system through a host bridge that connects the peripheral bus to a CPU local bus.
Each type of bus has a different set of standard protocols or rules that it uses to conduct the data transfers between the different devices and components connected to it. These protocols are designed into the bus and are called the "architecture" of the bus. Various protocols that may comprise a type of bus architecture are the bit-length of the data strings recognized by the bus, whether different signals are enabled when they are either low or high, whether data on the bus is multiplexed on one line or transmitted in parallel on several lines, or whether certain types of data are unacceptable and cause the information handling system to malfunction or "crash".
The bus architectures of CPU local buses and peripheral buses are normally different. The different architectures create communication problems when data must be transferred between a peripheral device connected to a peripheral bus, and the CPU or another component of the system connected to the CPU local bus. Since different bus architectures are involved in such a data transfer, data being transferred from the first bus architecture may not be in a form which is useable or intelligible by the second bus architecture.
Thus, an apparatus and method is needed to "translate" data that is transferred from one bus architecture to another. The hardware and logic used to translate data transferred between two different bus architectures is normally contained in the bridge through which the two different buses are connected. Accordingly, the host bridge connecting a CPU local bus and a peripheral bus must contain the logic and hardware that translates communications between the two buses and ensures that data is transferred between the two buses intelligibly.
One difference between the bus architectures of a CPU local bus and a peripheral bus is the reaction of the respective buses to the presence of non-contiguous data being transmitted on them. Non-contiguous data consists of bytes of enabled data separated by a byte, or bytes, of data that is not enabled. Not enabled, or disabled, data is data that is unintelligible and should be ignored and not transferred during the particular data transfer. Some types of peripheral buses and devices connected to these peripheral buses can transmit non-contiguous data without experiencing a malfunction. In contrast, transmission of non-contiguous data on a CPU local bus can cause the information handling system to crash or seriously malfunction.
Another difference between peripheral bus architecture and the architecture of the CPU local bus is that the CPU local bus can intelligibly transmit data in different bit lengths while peripheral buses may be limited to one standard bit length for data transmissions. Thus, the CPU local bus is compatible with components that are designed to transmit and receive data in various bit lengths. For example, a component that only transmits and receives data strings that are eight bits long can transmit or receive data when connected to a CPU local bus. Similarly, a 16-bit or 32-bit component can also use the CPU local bus for data transfers. The ability of the CPU local bus to accommodate data transfers in various bit lengths is called dynamic bus sizing.
In contrast, a peripheral bus may be limited to transmitting data strings of a standard bit length, such as 32 bits. Thus, a component connected to the CPU local bus that only transfers and accepts data in a bit length different from the standard bit length for data transmitted on a particular peripheral bus cannot communicate with peripheral devices connected to the peripheral bus without some type of intervening data translation.
Thus, it is an object of this invention to provide a method and apparatus that determines if data to be transmitted on a CPU local bus is non-contiguous and, if so, substitutes contiguous data for said non-contiguous data to ensure that the CPU local bus does not malfunction.
It is a further object of this invention to provide a method and apparatus that translates data transfers between a device connected to a peripheral bus and a component connected to the CPU local bus that is designed for a bit length of data different from the standard bit length of data in the architecture of the peripheral bus.
It is yet a further object of this invention to provide these methods and apparatus in the hardware that comprises a host bridge that connects the CPU local bus to the peripheral bus.